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 DAPDNA-IMS |
 - Accelerating Image Processing -
DAPDNA-IMS is a DRP that can change its hardware functionality in one clock (5 nano-seconds) thereby performing multiple functions that traditionally required multiple chips. The chip can change its functionality even when the system is in operation, adapting to changes in the environment as necessary. DAPDNA-IMS is highly tuned for various kinds of image processing, especially office automation applications. The chip includes useful functional components such as line buffers and Huffman decoding hardware accelerators. Targeting large volume markets, DAPDNA-IMS is priced competitively. |
Features
 DAPDNA architecture
PE structure suitable for image processing
 Arithmetic and bit operations
Bit-select (select data bit by bit from 2 inputs), bit rotate, mask, compare
16 bit input, 32 bit output multiply
32 bit shift, etc.
608K internal memory
Hardware accelerators for image processing
PEs for Huffman coding table lookup
Additional-bit decode function for applications such as JPEG decoding
Max 1GBytes of main memory
Office automation market, which includes products such as multi function printers, faces shorter lifecycles for the products, and at the same time, needs to satisfy customers who require customized products, leading to small lot productions. DAPDNA-IMS targets this difficult market with a highly flexible programmable logic chip based on the DAPDNA architecture. The DAPDNA architecture has been proven to be highly effective in image processing applications with its predecessor, DAPDNA-2, which has become the de facto processor in image processing for industrial inspection systems.
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| DAPDNA-IMS Specifications |
DAPDNA-IMS Specifications
| DAP |
32 bit RISC processor
8KB Instruction cache, 8KB Data cache |
| DNA |
·955 dynamically reconfigurable 16 bit PEs in a 2-D matrix
·3 DNA Configuration memory banks
- 1 foreground bank and 2 background banks
- Can load additional DNA Configurations from main memory |
| Ext. Interface |
Direct I/O |
200MHz (Max, sync to ext. clock), 16 bit, 4 ch I/O total 1.6Gbyte/s. Can be used to connect multiple DAPDNA-IMS chips |
| DDR2 SDRAM |
266MHz, 64 bit DDR2 SDRAM I/F total 4.25Gbyte/s, 1GB max |
| PCI Express |
PCI Express rev1.0a compliant (x4) |
| ROM |
Boot and Program Serial ROM (SPI) |
| Ext. Interrupt |
8 |
| Other |
UART, GPIO |
| Clock |
266MHz |
| Power |
3.3V(I/O) 1.8V(I/O) 1.2V(core) |
| Package |
TE-BGA, 1156 pin |
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