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| DAPDNA Architecture
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DAPDNA-2 dynamically reconfigurable processor is a dual-core processor, comprised of IPFlex's own high-performance RISC core (DAP), paired with the DNA, a dynamically reconfigurable two-dimensional processing element matrix. DAPDNA-2 is thus able to provide the processing power of hardware coupled with the flexibility of software. This revolutionary platform will redefine the very concept of "hardware."
DAP RISC core controls the processor's dynamic reconfiguration, while portions of an application that require high-speed data processing are handled by the PE Matrix, which provides flexible parallel and pipelined operation.
The PE Matrix is an array of 376 Processing Elements (PE) - comprised of computation units, memory, synchronizers, and counters. The PE Matrix circuitry can be reconfigured freely into the structure that is most optimal for meeting the needs of the application in demand.
DAPDNA Architecture
 DAP (Digital Application Processor)
 High-performance RISC processor
Controls the dynamic reconfiguration
DNA (Distributed Network Architecture)
Dynamically reconfigurable
Provides “virtual hardware”
Two-dimensional array of 376 Processing Elements (PEs)
Allows arbitrary configuration of the degree of parallelism and pipeline depth in accordance with the requirements of an application.
 Dynamically Reconfigurable Technology |
Multi-Function Processing
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Applications can be called and executed as needed. |
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Features can be selected and executed according to changes in operating conditions. |
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Combines the advantage of hardware-based, high-speed processing with the flexibility of implementing multiple functions on a single chip. |
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Time-Sliced Processing
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Algorithms can be sliced in time for execution. |
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As soon as one processing task is completed, the hardware immediately moves on to the next task. |
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Switching from one processing configuration to another takes only nanoseconds, providing functional flexibility while maintaining system performance. |
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| Large on-chip RAM |
Large on-chip memory reduces the need to access off-chip memory, a process which often becomes a performance bottleneck. This feature allows the DNA to provide the maximum possible parallel processing performance.
Since the memory is distributed throughout the processing array, there is plenty of available memory bandwidth.
| Direct I/O |
DAPDNA-2 has six channels of Direct I/O, which provides the interface for transferring data directly onto and out of the PE Matrix.
Each channel of Direct I/O is 32-bit wide and operates at the maximum DAPDNA-2 system clock frequency of 166 MHz, providing maximum I/O rate of 32 Gbps.
The Direct I/O can operate synchronously on the system clock, or can be controlled by an external clock at a different frequency.
For high performance applications, multiple DAPDNA-2 processors can be connected together through Direct I/O and integrated into a single system. The processor’s plentiful I/O bandwidth eliminates overhead in chip-to-chip communication.
Direct I/O can be also used to communicate directly with external devices, bringing data in for processing on the PE Matrix, bypassing the Bus Switch and memory interface.
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