July 13, 2006
IPFlex Inc.

Dynamically Reconfigurable Processor based Image Inspection Systems to Start
Operation in Multiple Factories

- IPFlex's DAPDNA-2 Dynamically Reconfigurable Processors Used for its Massively Parallel Image Processing Capability and Flexibility

July 12th, 2006 Tokyo, Japan. IPFlex Inc.  today announced factory-floor operation of image inspection systems powered by IPFlex's DAPDNA-2* Dynamically Reconfigurable Processors (DRP)** have started with several customers.

Industrial image inspection systems require the computing performance for the real-time processing of high-definition images, while keeping the processing flexibility to cater to changing operating conditions.  The requirement was difficult to fulfill with existing computing devices, but four inspection system vendors have started operations of IPFlex's DAPDNA-2 DRP-powered image inspection systems, for the device's unique and advantageous characteristics that fulfill market demands.   In addition, a mass production in network security market has also been started based on the DAPDNA-2 processor.  The network appliance will reap the benefits of hardware performance while keeping the flexibility, which are must in the face of increasing demand for network capacity with the constantly changing environment, such as new security attacks.   Year 2006 will see a few more mass productions powered by the DAPDNA series of DRPs in the industrial image inspection and network applications, as well as in the security camera application.   With the DAPDNA-FW II design tool, which has sold over 220 licenses as of June 2006, users can design high speed, massively parallel image processing engine using Data Flow C (DFC***) language.  Designed at the C abstraction level, users can extract hardware performance at a significantly shorter development time compared to existing acceleration solutions.

About IPFlex

IPFlex supplies high performance, multifunctional dynamically reconfigurable processors (DRP) based on its internationally patented DAPDNA technology.  IPFlex also provides development software, evaluation boards, and peripheral interface products for the processors.   IPFlex and its partners in the DAPDNA Partner Program together provide optimal solutions for customers in inspection systems, image processing, network security, and high performance computing.

About the DAPDNA-2 Dynamically Reconfigurable Processor

DAPDNA-2 is a multi-core processor, comprised of a high-performance RISC processor core, called the DAP, and the dynamically reconfigurable core, DNA, a two-dimensional array of 376 processing elements (PEs).  DAPDNA-2 can change its hardware configuration to provide the optimal circuitry for an application on demand. This configuration change can take place not only when the system is designed, but also during operation, dynamically, in a single clock cycle****, to meet the instantaneous change in the needs of applications implemented by the system.

Terminology

* DAPDNA: Digital Application Processor / Distributed Network Architecture. ** Dynamically Reconfigurable Processor (DRP): A processor capable of changing chip circuitry dynamically. *** DFC: Co-developed with Celoxica Ltd. **** a single clock cycle: One clock switching operation is possible by creating configuration information beforehand and storing in the background configuration banks.